Enhancing Side Channel Attack-Resistance of the STTL Combining Multi-Vt Transistors with Capacitance and Current Paths Counterbalancing

Authors

  • Vitor Gonçalves Lima, Ms. Universidade Federal do Rio Grande do Sul
  • Guilherme Paim, Eng. UFRGS | KIT - Karlsruher Institute für Technologie
  • Rodrigo Wuerdig Universidade Federal do Rio Grande do Sul
  • Leandro Mateus Giacomini Rocha, Eng. UFRGS | imec Belgium | KULeuven - Belgium
  • Leomar da Rosa Júnior, Dr. UFPel
  • Felipe Marques, Dr. UFPel
  • Vinicius Valduga de Almeida Camargo, Dr. UFPel
  • Eduardo Costa, Dr. UCPel
  • Rafael Soares, Dr. UFPel
  • Sergio Bampi, Dr. UFRGS

DOI:

https://doi.org/10.29292/jics.v15i1.100

Keywords:

Hardware Security, Side Channel Attacks, Cryptography, Circuit Topology, Balanced Paths, Multi-Vt Transistors

Abstract

Differential power analysis (DPA) exploits the difference between the instantaneous power of the circuit arches transitions to stole the state as information aiming to unveil the cryptographic key. Secure triple track logic (STTL) is a circuit-level countermeasure to DPA attacks based on dual-rail precharge logic (DPL). STTL is robust to attacks due to the delay in an insensitive feature that mitigates the logic glitches generated by the different path delays that lead to the logic gate inputs until they stabilize. The main STTL drawback, however, is the asymmetry of the transistor topology. Asymmetry causes unbalanced internal capacitances and different internal paths for the current flow, and DPA exploits it as a source of information leakage. Our work proposes three circuit topologies, combining multi-Vt transistors with a circuit counterbalancing strategy, aiming to improve the STTL DPA attack-resistance. Data encryption standard substitution-box circuit, designed in a TSMC 40 nm CMOS process, is our application case study to evaluate the DPA attack-resistance. Results gathered at the application-level show that our proposals outperform DPA attack-resistance of the prior work.

Author Biographies

Guilherme Paim, Eng., UFRGS | KIT - Karlsruher Institute für Technologie

Guilherme Paim received the five-year engineering degree -- as fisrt ranked -- in Electronics Engineering from the Federal University of Pelotas, Brazil, in 2015. He is a Ph.D. candidate at the Federal University of Rio Grande do Sul, Porto Alegre, Brazil. Currently, he is with the Karlsruhe Institute of Technology as a visiting researcher with a Ph.D. sandwich scholarship. His research interests are Approximate Computing, Low-power VLSI architectures, Arithmetic Operators, Video Coding, Approximate Digital Signal Processing, Neural Networks Accelerators, Side-channel attack-resistant circuits for Cryptography.

Leandro Mateus Giacomini Rocha, Eng., UFRGS | imec Belgium | KULeuven - Belgium

Leandro Mateus Giacominni Rocha received a five-year engineering degree in Computer Engineering from the Federal University of Rio Grande do Sul, Porto Alegre, Brazil, in 2016. He also obtained an engineer degree in Electronic Integrated Systems from the Grenoble Institute of Technology, France, in 2015 as part of a double degree program. He is a Ph.D. candidate at the Federal University of Rio Grande do Sul, Porto Alegre, Brazil. Currently, he is a visiting PhD student at KUL and imec working on neural network hardware accelerators for portable devices. His research interests are low-power VLSI architectures, Approximate Computing, Neural Networks Accelerators, Arithmetic Operators, Digital Signal Processing, Machine Learning, Multipliers.

Eduardo Costa, Dr., UCPel

Eduardo Antonio César da Costa received the five-year engineering degree in Electrical Engineering from the University of Pernambuco, Recife, Brazil, in 1988, the M.Sc. degree in electrical engineering from the Federal University of Paraíba, Campina Grande, Paraíba, Brazil, in 1991, and the Ph.D. degree in computer science from the Federal University of Rio Grande do Sul, Porto Alegre, Brazil, in 2002. Part of his doctoral work was developed at the Instituto de Engenharia de Sistemas Computadores (INESC-ID), Lisbon, Portugal. He is currently a full professor at the Catholic University of Pelotas (UCPel), Pelotas, Brazil. He is co-founder and coordinator of the Graduate Program on Electronic Engineering and Computing at UCPel. His research interests are VLSI architectures and low-power design.

Sergio Bampi, Dr., UFRGS

Sergio Bampi received the Electronics Engineer and B.Sc. Physics degrees from Federal University of Rio Grande do Sul (1979). He received the MSEE and Ph.D. in Electrical Engineering degrees from Stanford University in 1982 and 1986, respectively. He is a full professor at the Informatics Institute at the Federal University of Rio Grande do Sul, Brazil, which he joined in 1981. He was a former president of the Brazilian Microelectronics Society, of the FAPERGS Brazilian research funding agency, and CEITEC Technical Director. He is a senior member of IEEE and was a distinguished lecturer of IEEE CAS Society (2009-2010). He has published more than 360 research papers in the fields of CMOS Analog, Digital and RF Design, Video Coding algorithms and hardware architectures, and MOS devices. He was Technical Program Chair of SBCCI (1997, 2005), IEEE LASCAS (2013), SBMICRO Congress (1989), and served on TPC Committees of ICCAD, ICCD, SBCCI, ICM, LASCAS, VLSI-SoC and many other international conferences.

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Published

2020-05-26

Issue

Vol. 15 No. 1 (2020): Journal of Integrated Circuits and Systems

Section

Regular Papers