Design of a Programmable Gain Amplifier (PGA) for Bluetooth Low Energy (BLE) in 0.13 um CMOS




Receiver, PGA, Low power, Common-source, CMFB, Amplifier


Programmable Gain Amplifiers (PGA's) are circuits capable of conveniently changing their gain to address various levels of amplification. Knowing this, the topology proposed in this work takes a source degenerated first stage, a common-source with resistive load second stage, and a gm boosting circuit interface to realize a PGA that has low power consumption and low area. The design developed was able to achieve a maximum power dissipation of 103.1 uW, a minimum bandwidth of 5.59 MHz, a maximum noise of 32.01 nV/sqrt(Hz), and a gain range of 2.31 - 19.84 dB. Each differential output of the circuit is loaded with 700 fF, which is the estimated load for the hypothetical following block, the Analog-to-Digital Converter (ADC). Furthermore, the supply voltage of the circuit is 1 V and the design was undertaken on Global Foundrie's 130 nm technology. The phase margin of the core circuit is no greater than 100.3˚  and no less than 49˚  . The circuit which design is described in this work is intended to be within the receiver (RX) sub-domain of a Bluetooth Low-Energy (BLE) system, which finds applications on the IoT and healthcare industries, for instance.