Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures

Authors

  • André Sapper Catholic University of Pelotas (UCPel) - Brazil
  • Guilherme Paim Federal University of Rio Grande do Sul (UFRGS) - Brazil
  • Eduardo Antônio César da Costa Catholic University of Pelotas (UCPel) - Brazil
  • Sergio Bampi Federal University of Rio Grande do Sul (UFRGS) - Brazil

DOI:

https://doi.org/10.29292/jics.v16i2.226

Keywords:

Fast Fourier Transform, Low-`Power, CORDIC, Clock-gating

Abstract

This work explores hardware-oriented optimizations for the CORDIC (COordinate Rotation Digital Computer) algorithm investigating the power-efficiency improvements employing N-point Fast Fourier Transform (FFT) hardware architectures. We introduced three hardware-oriented optimizations for the CORDIC: (a) improving the signal extension, (b) removing the angle accumulation and (c) eliminating the redundancies in the iterations, both unnecessary when processing the FFT processing. Fully sequential FFT architectures of 32, 64, 128, and 256 points were synthesized employing ST 65 nm standard cell libraries. The results show up to 38% of power savings on average when using our best CORDIC optimization proposal to the FFT architecture comparing to the explicit multiply-based butterfly version. Moreover, when combining our best CORDIC optimization with the clock-gating technique, the power savings rises to 78.5% on average for N-point FFT.

Additional Files

Published

2021-08-15