Design Considerations of a Nonvolatile Accumulator Based 8-bit Processor

Abstract

The rise of the Internet of Things (IoT) and the constant growth of portable electronics have leveraged the concern with energy consumption due to the use of batteries in these devices. The nonvolatile memory (NVM) emerged as a solution to mitigate the problem due to its ability to retain data on sleep mode without a power supply. Nonvolatile processors (NVPs), in turn, may further improve energy saving, by making use of nonvolatile flip-flops (NVFFs) that store system state in parallel, allowing the device to be turned off when idle and resume execution instantly after power-on. This work describes the initial steps to implement a nonvolatile version of Neander, a hypothetical processor created for educational purposes. First, we implemented Neander in Register Transfer Level (RTL), separating the combinational logic from the sequential elements. Then, the latter were replaced by transistor-level descriptions of
volatile flip-flops. We then validated this implementation by employing a mixed-signal simulation over a set of benchmarks. Results shown the expected behavior for the whole instruction set. Then, we implemented MTJ-based non-volatile flip-flops in circuit-level, using an open-source MTJ model. These elements were exhaustive validated using electrical simulations. With these results, we intend to carry on the implementation and fully equip our processor with nonvolatile features such as instant wake up.