Asynchronous AES Crypto-Processor Including Secured and Optimized Blocks

Abstract

This paper presents the first study of an asynchronous AES architecture compliant with the NIST standard. It exploits the fundamental properties of quasi delay insensitive asynchronous circuits. First, 1 to N encoding is extensively used in order to minimize hardware cost, thus optimizing area and speed. Most importantly, it is shown how the quasi delay insensitive logic style gives the opportunity to design balanced architectures, particularly well suited to improve differential power analysis resistance. Indeed, the proposed design methodology enables the generation of logic circuits which always involve a constant number of logical transitions, independently of data values processed by the circuit. Based on a 32-bit data-path, a balanced and optimized QDI asynchronous architecture of the AES is described. In addition, several architecture trade-offs are considered, and their area and speed estimated. Simulation results show that with the proposed design approach, throughputs ranging from 36 Mbit/s to more than 569 Mbit/s can be achieved, well suited to target smart-card applications.