Core Communication Interface for FPGAs

Authors

  • José Carlos Palma
  • Aline Vieira de Mello
  • Leandro Möller
  • Fernando Moraes
  • Ney Calazans

DOI:

https://doi.org/10.29292/jics.v1i1.254

Keywords:

IP cores, SOC, FPGA, reconfiguration

Abstract

The use of pre-designed and pre-verified hardware modules, also called IP cores, is an important part of the effort to design and implement complex systems. However, many aspects of IP core manipulation are still to be developed. This paper presents an approach to solve problems related to the dynamic interconnection of hard IP cores. The approach targets system-on-a-chip designs build in a single FPGA device. The paper proposes a communication interface that allows IP cores replacement during the FPGA normal operation. The same interface also allows the communication among distinct IP cores to take place.

Additional Files

Published

2020-11-16