A Fast-Response Charge-Pump Gate Driver Applied to Linear Regulation

Authors

  • André L. R. Mansano
  • Jader A. De Lima
  • Jacobus W. Swart

DOI:

https://doi.org/10.29292/jics.v5i1.306

Keywords:

Gate driver, Charge-pump, Switched-capacitor converters

Abstract

This paper presents a compact charge-pump gate driver (CPGD) that dynamically adjusts the driving voltage VGS_SW of power switches, following stringent load transients in amplitude and duration. Owing to its simple topology, the CPGD responsively sustains regulation of the charge-pump (CP) output voltage VOUT within the range [2.4V, 3.0V] during transient load, while consuming only tens of μA. Contrary to driving techniques that depend on the settling of VOUT before adjusting VGS_SW, the CPGD instantaneously compares VOUT to a reference VREF and optimally sets VGS_SW. The circuit shows low sensitivity with switching frequency fsw across a broad range [50KHz fsw 1MHz]. Simulations with PSPICE and Bsim3v3 models attest the CPGD performance at extreme scenarios of a light and heavy load current ILOAD. For a 20μs-step of ILOAD from 0 to 20mA, the CPGD takes only 20μs to raise VGS_SW from 1.0V to 4.75V. The entire CP regulator was prototyped on a standard 0.35μm CMOS fabrication process, with the CPGD occupying an area of 0.014μm2. Experimental results match closely both DC and transient the expectations for CPGD. The driver features consumption below 475μW and complies with a low-voltage supply, such as1.5V-batteries.

Additional Files

Published

2020-11-21