Packet-driven General Purpose Instruction Execution on Communication-based Architectures

Abstract

In the last few years, the development of Multi-Core architectures was driven by the crescent advance in integration technology. In this scenario, when the number of cores increases, problems found on shared communication media, such as busses, can be addressed by using a network approach. This paper proposes the usage of communication capabilities of Networks-on-Chip (NoCs) to execute general purpose instructions. The main idea behind this approach is to allow networks-on-chip architectures to execute general purpose instructions inside each router architecture. This paper addresses the main architectural concerns involved on creating datapaths for routers as well as the programming model suggested to pack instructions on messages. Simulation results on two case studies illustrate the benefits of the proposed architecture when compared to an equivalent NoC-based MP-SoC.