A Design Methodology Using the Inversion Coefficient for Low-Voltage Low-Power CMOS Voltage References

Authors

  • Dalton Colombo
  • Christian Fayomi
  • Frederic Nabki
  • Luiz F. Ferreira
  • Gilson Wirth
  • Sergio Bampi

DOI:

https://doi.org/10.29292/jics.v6i1.333

Keywords:

CMOS Voltage Reference, Analog Design Methodology, Inversion Coefficient, Low Voltage Design, Low Power Design

Abstract

This paper presents an analog design methodology, which uses the selection of the inversion coefficient of MOS devices, to design low-voltage and low-power (LVLP) CMOS voltage references. The motivation of this work comes from the demand for analog design methods that optimize the sizing process of transistors working in subthreshold operation. The advantage of the presented method – compared to the traditional approaches for circuit design – is the reduction of design cycle time and the minimization of simulation iterations when the proposed equations are used. As a case study, a LVLP voltage reference based on subthreshold MOSFETs with a supply voltage of 0.7 V was designed in a 0.18-μm CMOS technology.

Additional Files

Published

2020-12-27

Issue

Section

Special Section on Best SBCCI2010 Papers