HdSC: A Fast and Preemptive Modeling for on Host HdS Development

Authors

  • Bruno Prado
  • Edna Barros
  • Thiago Figueredo
  • André Aziz

DOI:

https://doi.org/10.29292/jics.v7i1.356

Keywords:

HdS, Modeling, Preemptive, Simulation, Instruction Set Simulator

Abstract

In modern embedded systems, the Hardware-dependent Software (HdS) plays a critical role due to its processor and platform dependency, such as device drivers and boot initialization. To support HdS development starting in an initial system design phase, fast and accurate preemptive processor models should be provided for simulating the software. These models should provide a register level interface to enable a compatible programming view on the host machine environment. This paper presents a strategy for processor modeling that enables HdS development, using the host machine tool chain. The proposed approach supports the specification of platform components, such as processor, software and devices accessed through the data bus and interruption interfaces. An adaptive technique for timing estimation is being proposed, which is very accurate and show a high simulation performance. Supporting the device driver development and interruption service routines, these two features can be implemented and simulated at an early system design phase and requiring no Instruction Set Simulator (ISS). This ISS model would be required only for performance and accuracy comparison purposes. Experimental results show that the virtual platform specified using this proposed approach can perform faster (up to 760x speed up) and high accurate (up to 12%) software simulation on native host environment.

Additional Files

Published

2020-12-27

Issue

Section

Special Section on Best SBCCI2011 Papers