SOI n- and pMuGFET devices with different TiN metal gate thickness and crystallographic orientation of the sidewalls

Authors

  • Michele Rodrigues
  • Milene Galeti
  • Nadine Collaert
  • Eddy Simoen
  • Cor Claeys
  • João Antonio Martino

DOI:

https://doi.org/10.29292/jics.v7i2.362

Keywords:

TiN, High k, Analog performance, MuGFETs

Abstract

This work presents an analysis of SOI p- and nMuGFET devices with different TiN metal gate electrode thickness for rotated and standard structures.Thinner TiN metal gate allows achieving a higher intrinsic voltage gain in spite of the reduced variation observed of the gm/IDS characteristics. This effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. Even with the larger mobility of the rotated nMuGFET devices when compared with the standard ones, the larger output conductance degradation resulted in an almost similar intrinsic voltage gain. P-channel devices, when implemented on the rotated layout, offer a lower intrinsic voltage gain.The GIDL current was also analyzed on these devices, indicating to be larger in thinner metal gate and rotated configuration.

Additional Files

Published

2020-12-27

Issue

Section

Special Section on Best SBMicro2011 Papers