Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors
Keywords:Junctionless Nanowire Transistors, Analytical Model, Subthreshold Slope, Drain Induced Barrier Lowering
Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.