A low-power 10-bit 6.66 MS/s CMOS SAR ADC with built-in digital calibration dedicated to Wireless Sensor Networks applications
DOI:
https://doi.org/10.29292/jics.v13i3.4Keywords:
ADC, low-power, SAR, CMOS, self-calibratorAbstract
In this paper, an energy-efficient SAR ADC for IoT applications is presented. The proposed ADC relies on a built-in calibration circuit to improve accuracy and introduces an original DAC that merges the concepts of binary-weighted and C/2C arrays in order to achieve a favorable trade-off between area, accuracy and power consumption. The system consumes 58 µW per conversion cycle sampling at a frequency of 6.66 MHz with an SNDR of 49.78 dB for a 1MHz input signal. With an ENOB of 8 bits, the resulting FOM is 34fJ/conversion-step.
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Published
2018-12-12
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Section
Regular Papers