Gate-Oxide Voltage Overstress Treatment in Charge Pump Circuits for Standard CMOS Technologies

Abstract

Charge pump circuits operating at voltage levels above that of the power supply usually suffer from gate-oxide voltage overstress. Such reliability problem has become a concern especially as the gate-oxide thickness is scaled down. Devising charge pump circuits that avoid such a problem is far simpler for CMOS triple-well technologies than for standard technologies, nevertheless fabrication costs are higher. Two approaches are usually applied to eliminate gate-oxide overstress in charge pumps designed for standard CMOS technologies, the first is multiple phase control, and the second is dual phase control with doubled voltage swing. The latter has been shown to produce more power efficient circuits, however solutions using such approach still present gate-oxide overstress in some transistors. In this work, it is shown that a slight change in some of the circuit connections is able to ultimately overcome the problem. Moreover, experimental results have shown that such circuit topology can reach a voltage multiplication efficiency of about 98 %.