A Synthesizable BCH Decoder For DVB-S2 Satellite Communications

Authors

  • Cesar G. Chaves
  • Eduardo R. de Lima
  • Jacqueline G. Mertes

DOI:

https://doi.org/10.29292/jics.v10i3.420

Keywords:

BCH, Error-correction, DVB-S2, VLSI, FPGA

Abstract

This paper presents the design of a BCH Decoder for digital satellite TV Communications. It includes an architecture design specification, as well as the results of FPGA prototyping and of the logical and physical synthesis in 65nm CMOS. Moreover, it can be used as a basis for BCH Decoder designs for other kind of communications or even storage error correction.

Additional Files

Published

2020-12-28