Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs

Authors

  • Alberto V. Oliveira
  • Paula Ghedini Der Agopian
  • João Antonio Martino
  • Eddy Simoen
  • Cor Claeys
  • Hans Mertens
  • Nadine Collaert
  • Aaron Thean

DOI:

https://doi.org/10.29292/jics.v11i1.424

Keywords:

Ge pMOSFET, Dynamic threshold voltage control, I-V Hysteresis, Gate stack layer, Intrinsic voltage gain

Abstract

One of the main challenging issues for germanium (Ge) devices is the gate stack engineering which determines the interface state density (NIT) and the associated channel/oxide interface quality. This paper shows how this issue can play a role in p-channel Ge MOSFETs considering both the operation mode, i.e., comparing conventional, dynamic threshold voltage (DT, where VBS = VGS) and enhanced dynamic threshold voltage (eDT, where VBS=k*VGS) modes, and the main analog parameters like the Early voltage (VEA) and intrinsic voltage gain (AV). Moreover, the impact of different HfO2/Al2O3 gate stack thicknesses is under evaluation. Although the thinnest Al2O3 layer degrades all evaluated parameters, specifically: lower VEA and AV, higher drain current hysteresis and subthreshold swing (SS) due to the higher NIT, the dynamic threshold voltage showed to be an effective mode to strongly minimize the hysteresis effects and improves up to 60% in eDT (k = 2) mode compared to the conventional mode (k = 0), thanks to the dynamic threshold voltage reduction.

Additional Files

Published

2020-12-28