Low Temperature Sensitivity CMOS Transconductor Based on GZTC MOSFET Condition

Authors

  • Pedro Toledo
  • Hamilton Klimach
  • David Cordova
  • Sergio Bampi
  • Eric Fabris

DOI:

https://doi.org/10.29292/jics.v11i1.427

Keywords:

CMOS, Analog integrated circuits, Low temperature sensitivity transconductors, ZTC condition

Abstract

Complementary Metal Oxide Semiconductor (CMOS) Transconductors, or Gm cells, are key building blocks to implement a large variety of analog circuits such as adjustable filters, multipliers, controlled oscillators and amplifiers. Usually temperature stability is a must in such applications, and herein we define all required conditions to design low thermal sensitivity Gm cells by biasing MOSFETs at Transconductance Zero Temperature Condition (GZTC). This special bias condition is analyzed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are designed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits have been simulated in a 130 nm CMOS commercial process, resulting in improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/oC.

Additional Files

Published

2020-12-28