Hardware Implementation for the HEVC Fractional Motion Estimation Targeting Real-Time and Low-Energy
Keywords:Video coding, Hardware design, Real-time processing, HEVC Standard, Fractional Motion Estimation
This paper presents an energy-aware and high-throughput hardware design for the Fractional Motion Estimation (FME) compliant with the High Efficiency Video Coding (HEVC) standard. An extensive software evaluation was performed to guide the hardware design. The adopted strategy mainly consists in using only the four squareshaped Prediction Unit (PU) sizes rather than using all 24 possible PU sizes in the Motion Estimation (ME). This approach reduces about 59% the total encoding time and, as a penalty, it leads to an increase of only 4% in the bit rate for the same image quality. Together with this simplification, a multiplierless approach, algebraic optimizations and low-power techniques were applied to the hardware design to reduce the hardware-resource usage and the energy consumption, maintaining a high processing rate. The architecture was described in VHDL and the synthesis results for ASIC 45nm Nangate standard cells demonstrate that the developed architecture is able to process Ultra-High Definition (UHD) 2160p videos at 60 frames per second (fps), with the lowest power consumption and the lowest hardware-resource usage among the related works.