Fault Injection on a Mixed-Signal Programmable SoC with Design Diversity Mitigation

Authors

  • Carlos J. G. Aguilera
  • Cristiano P. Chenet
  • Tiago R. Balen

DOI:

https://doi.org/10.29292/jics.v11i3.443

Keywords:

Fault Injection, Soft-Error, Fault Tolerance, Triple Modular Redundancy, Design Diversity, Mixed-Signal, Single Events, Data Converters, Programmable System-on-Chip

Abstract

This paper presents an approach for runtime software-based fault injection, applied to a commercial mixed-signal programmable system-on-chip (PSoC). The fault-injection scheme is based on a pseudo-random sequence generator and software interruption. A fault tolerant data acquisition system, based on a design diversity redundant scheme, is considered as case study. The fault injection is performed by intensively inserting bit flips in the peripherals control registers of the mixed-signal PSoC blocks, as well as in the SRAM memory of the device. Results allow to evaluate the applied fault tolerance technique, indicating that the system is able to tolerate most of the generated errors. Additionally, a high fault masking effect is observed, and different criticality levels are observed for faults injected into the SRAM memory and in the peripherals control registers.

Additional Files

Published

2020-12-28