Bias Stress Effects in Low Temperature Amorphous Hf-In-ZnO TFTs Using RF-sputtering HfO2 as High-k Gate Dielectric

Authors

  • C. A. Pons-Flores
  • I. Hernández
  • I. Garduno
  • I. Mejía
  • M. Estrada

DOI:

https://doi.org/10.29292/jics.v12i1.446

Keywords:

AOSTFTs, stability, contact resistance, hump, bias stressing

Abstract

In this work we analyze the electrical performance, contact resistance and the effects of positive and negative gatebias stress of Hf-In-ZnO/HfO2 thin film transistors. Devices were fabricated using RF-magnetron sputtering at room temperature and fully patterned, with operation voltage below 6 V. Devices with drain-currents up to 2x10-6 A and threshold voltages of ~2 V were analyzed under negative and positive gate bias stress. Devices under negative gate-bias stress showed a slightly threshold voltage shift due to the transistor channel is depleted of electrons at the channel/dielectric interface. Devices under positive gate-bias stress, showed threshold voltage shifts in the negative direction due to the reversible charge/discharge effect of the electrons in pre-existing high-k HfO2 bulk traps. Positive gate-bias stress does not cause any degeneration, since stressed devices tend to recover after 5 mins.

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Published

2020-12-28