A Fast Monolithic 8-2 Adder Compressor Circuit

Authors

  • Thomas Fontanari Federal University of Rio Grande do Sul
  • Guilherme Paim Federal University of Rio Grande do Sul
  • Leandro Mateus Giacomini Rocha
  • Gustavo Madeira Santana
  • Eduardo Antônio César da Costa Catholic University of Pelotas
  • Sergio Bampi Federal University of Rio Grande do Sul

DOI:

https://doi.org/10.29292/jics.v14i1.51

Keywords:

Fast, Monolithic, 8-2 Adder Compressor

Abstract

Adder compressor architectures have been widely used in multipliers and have recently achieved improvements over conventional approaches in the computation of multiple modules, such as transform blocks, in the context of video coding. This paper reviews four different state-of-the-art 8-2 adder compressor architectures and proposes a novel one. A 65 nm commercial standard cell library was used to synthesize the compressors. The results show that, as a consequence of a shorter critical path, our circuit presented significant improvements regarding maximum operational frequency, while still maintaining similar results for power dissipation. Our circuit also managed to achieve a smaller circuit area, as a result of a more straightforward net interconnection.

Author Biographies

Eduardo Antônio César da Costa, Catholic University of Pelotas

Eduardo Costa received the five-year engineering degree in Electrical Engineering from the University of Pernambuco, Recife, Brazil, in 1988, the M.Sc. degree in Electrical Engineering from the Federal University of Paraiba, Campina Grande, Para\´iba, Brazil, in 1991, and the Ph.D. degree in computer science from the Federal University of Rio Grande do Sul, Porto Alegre, Brazil, in 2002. Part of his doctoral work was developed at the Instituto de Engenharia de Sistemas Computadores (INESC-ID), Lisbon, Portugal. He is currently a full professor at the Catholic University of Pelotas (UCPel), Pelotas, Brazil. He is co-founder and coordinator of the Graduate Program on Electronic Engineering and Computing at UCPel. His research interests are VLSI architectures and low-power design.

Sergio Bampi, Federal University of Rio Grande do Sul

Sergio Bampi received the Electronics Engineer and B.Sc. Physics degrees from the Federal University of Rio Grande do Sul (1979). He received the MSEE and Ph.D. in Electrical Engineering degrees from Stanford University in 1982 and 1986, respectively. He is a full professor at the Informatics Institute at the Federal University of Rio Grande do Sul, Brazil, which he joined in 1981. He was a former president of the Brazilian Microelectronics Society, of the FAPERGS Brazilian research funding agency, and CEITEC Technical Director. He is a senior member of IEEE and was a distinguished lecturer of IEEE CAS Society (2009-2010). He has published more than 380 research papers in the fields of CMOS Analog, Digital and RF Design, Video Coding algorithms and hardware architectures, and MOS devices. He was Technical Program Chair of SBCCI (1997, 2005), IEEE LASCAS (2013), SBMICRO Congress (1989), and served on TPC Committees of ICCAD, ICCD, SBCCI, ICM, LASCAS, VLSI-SoC, and many other international conferences.

Downloads

Published

2019-04-29

Issue

Vol. 14 No. 1 (2019): Journal of Integrated Circuits and Systems

Section

Regular Papers