Electrical Evaluation of Logic Network Generation Methods for On-the-Fly Supergate Design

Authors

  • Henrique Kessler Federal University of Pelotas (UFPel) - Brazil
  • Marcello Muñoz Federal University of Pelotas (UFPel) - Brazil
  • Plínio Finkenauer Federal University of Pelotas (UFPel) - Brazil
  • Leomar da Rosa Jr. Federal University of Pelotas (UFPel) - Brazil
  • Vinícius Camargo Federal University of Pelotas (UFPel) - Brazil

DOI:

https://doi.org/10.29292/jics.v16i3.527

Keywords:

Cell design automation, static CMOS complex gate, transistor network, electronic design automation

Abstract

Recent developments in electronic design automation tools vastly reduce the design cost of supergates, enabling an alternative approach to logic synthesis. Despite many design strategies targeting the transistors network in supergates, their comparisons are often limited to metrics such as the number of transistors used or circuit total stack, lacking an in-depth electrical evaluation. This work presents an electrical comparison of three different design techniques. The study evaluates the 3,982 logic functions of the 4 input P-class, and it shows that topologies that optimize both pull-up and pull-down networks individually presented better overall electrical characteristics. The results also suggest that reducing the logic gate stack or the number of transistors does not necessarily lead to better performance. Additionally, the results show that a single network generation method can yield in a comparatively good design or in a supergate that could achieve 50% smaller propagation delay and power dissipation by another approach, pointing to a strong dependency between the effectiveness of the method and the logic function being implemented.

Additional Files

Published

2021-12-31