A Low-cost Fault Tolerance Method for ARM and RISC-V Microprocessor-based Systems using Temporal Redundancy and Approximate Computing through Simplified Iterations

Authors

  • Alexander Aponte-Moreno Universidad Nacional de Colombia
  • Felipe Restrepo-Calle Universidad Nacional de Colombia
  • Cesar Pedraza Universidad Nacional de Colombia

DOI:

https://doi.org/10.29292/jics.v16i3.539

Keywords:

Approximate Computing, Reliability, Fault Tolerance, RISC-V, ARM

Abstract

Approximate Computing techniques have been successfully used to reduce the overhead associated with redundancy in fault-tolerant system designs. This paper presents a fault tolerance method to reduce the execution time overhead of the well-known Time Redundancy technique by means of an improvement proposed for the Approximate Computing software-based technique known as loop perforation. Time Redundancy is a software-based fault tolerance technique that involves executing replicas of a task at different times. We propose to approximate the tasks to be executed using a new approximate computing technique based on loop perforation, i.e., simplified iterations. The novelty of this method is the combined use of the fault tolerance technique, temporal redundancy, jointly with the new proposed Approximate Computing technique, simplified iterations. The proposal is validated through simulation-based fault injection campaigns on several test programs for the ARM and RISC-V microprocessor architectures. Experimental results verified not only the applicability of the proposal in different architectures, but also its effectiveness, showing a good trade-off between reliability, error and overhead. Results showed that using the proposed method, a normalized mean work to failure (MWTF) up to 5.28× was obtained with approximation errors lower than those obtained using the traditional loop perforation technique.

Additional Files

Published

2021-12-31 — Updated on 2022-04-02

Issue

Section

Special Issue on Hardware and Software Fault Tolerance