Synthesis of Steel-ASIC, a RISC-V Core

Authors

  • Rafael da Silva Federal University of Rio Grande do Sul (UFRGS) - Brazil
  • Vin´ıcius dos Santos Federal University of Rio Grande do Sul (UFRGS) - Brazil
  • F´abio Petkowicz Federal University of Rio Grande do Sul (UFRGS) - Brazil
  • Rafael Calc¸ada Federal University of Rio Grande do Sul (UFRGS) - Brazil
  • Ricardo Reis Federal University of Rio Grande do Sul (UFRGS) - Brazil

Keywords:

VLSI, RISC-V, Steel Core, ASIC, Microprocessor

Abstract

It is presented the design flow of an ASIC version of STEEL, a RISC-V microprocessor developed at UFRGS. The microprocessor core called STEEL implements the RV32I and Zicsr instruction sets of the RISC-V specifications. The whole process entails logical and physical synthesis, using the X-Fab 180 nm, which relies on the Cadence EDA framework. The ASIC circuit operates with a maximum frequency of 19.61 MHz and the estimates obtained from the physical synthesis indicates a power consumption of 10.09 mW.

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Published

2022-09-17

Issue

Section

Selected Paper from Microelectronics Students Forum 2021