Effects of Thermal Annealing on the Density of States in Low Voltage Operating Range, High Mobility, Hf-In-ZnO/HfO2 TFTs Fabricated at Temperatures below 200 oC
Keywords:Low temperature AOSTFT process, passivated a-HIZO TFTs, HfO2 gate dielectric, density of states, interface trap density.
In this paper, we report the effects of thermal annealing on Poly(methyl methacrylate) (PMMA) passivated, bottom gate thin film transistors, with amorphous hafnium oxide (HfO2) as gate dielectric and amorphous hafnium-indium-zinc oxide (a-HIZO) as semiconductor, fabricated at temperatures below 200 oC. It is shown that TFTs, with VTH =0.55 V, mFE>250 cm2/Vs, SS=200 mV/dec corresponding to Dit= 1x1012 cm-2eV-1 and Ion/Ioff>107, can be obtained, using a thermal annealing at 200 oC in N2, after the semiconductor layer is deposited. The dielectric constant of the HfO2 layer deposited by RF sputtering was 19.5, allowing devices to work within the operating voltage range of 2 V. An important increase of the field effect mobility is obtained, combining a high-k gate dielectric and a high carrier concentration a-HIZO layer, with a lower density of localized states.
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