Properties and Design of CMOS Thyristor Delay Elements

Authors

  • Ian Christian Fernandez University of the Philippines Diliman - Philippines
  • Maria Theresa de Leon University of the Philippines Diliman - Philippines
  • Anastacia Alvarez University of the Philippines Diliman - Philippines
  • John Richard Hizon University of the Philippines Diliman - Philippines
  • Marc Rosales University of the Philippines Diliman - Philippines

DOI:

https://doi.org/10.29292/jics.v17i1.580

Keywords:

CMOS Thyristors, Delay Elements, Sensitivity

Abstract

The CMOS thyristor delay element and its basic operation are presented in this paper. Six variations of the thyristor design developed over the years to extend the delay length, to improve the consistency of the delay, or to control the sensitivities of the delay are also discussed. This includes the complementary thyristor, the thyristor without the current source, the thyristor with threshold elevation, the thyristor with opposing current source, the single-ended thyristor, and the thyristor-type feedback delay element. Design considerations common to all CMOS thyristors are also discussed to provide insights on topology selection, capacitive loading, and transistor sizing.

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Published

2022-04-30

Issue

Section

Special Issue on Analog and Mixed-Signal Integrated Circuits