Surface versus Performance Trade-offs: A Review of Layout Techniques


  • Pietro Maris Ferreira Université Paris-Saclay and Sorbonne Université - France
  • Emilie Avignon-Meseldzija Université Paris-Saclay and Sorbonne Université - France
  • Philippe Bénabès Université Paris-Saclay and Sorbonne Université - France
  • Francis Trélin Université Paris-Saclay and Sorbonne Université - France



surface constraints, layout techniques, performance compromise, icLayoutRender


Selecting the relevant layout techniques is a key point to obtain a high-performance integrated circuit. Most of the common layout techniques, beside allowing the improvement of performance, also leads to an area overhead. Moreover, this area overhead is generally not accurately evaluated. It is proposed in this review to analyze and to evaluate the surface versus performance trade-off in three types of circuits : digital, low-frequency and radiofrequency analog circuits. Each circuit is post-layout simulated using BiCMOS SiGe 55 nm technology from STMicroelectronics. The first analysis evaluates the surface, power consumption and speed trade-off in a digital circuit implementing a 16-bit gray counter, when selecting different combinations of gates from the B55 digital library. The second analysis focuses on the implementation of an accurate capacitor ratio for switched capacitor circuits and quantifies the surface versus accuracy performance. The third analysis evaluate the performance trade-off for six different layout techniques applied on a negative resistor required for a VCO.






Special Issue on Analog and Mixed-Signal Integrated Circuits