Real-Time and Low-Power HEVC Deblocking Filter Architecture Targeting 8K UHD @ 60fps Videos
Keywords:Video coding, HEVC, Deblocking Filter, Hardware design, High resolution videos
This paper presents a low-power and high-throughput Deblocking Filter (DBF) hardware architecture for the High Efficiency Video Coding (HEVC) standard. The architecture implements the three HEVC deblocking filtering modes, namely: (i) normal filter, (ii) strong filter and (iii) chroma filter. The designed DBF architecture is able to process 64 samples per clock cycle, considering luminance and chrominance components. The architecture was described in VHDL and synthesized targeting the CMOS standard-cell TSMC 40nm library. The power results were reached with real input samples extracted from the HEVC reference software. Synthesis results show that the DBF design, when running at 124.4MHz, can reach a throughput of 60 frames per second (fps) for a 7680×4320 (8K UHD) video resolution. At this frequency, the DBF design presented a low power dissipation of 4.73mW. The presented DBF hardware surpasses all related works in terms of throughput and power dissipation and is the unique solution able to real-time processing of 8K UHD videos at 60 frames per second.