Silicon Nanowire Technologies: brief review, home-made solutions and future trends

Authors

  • Lucas Stucchi-Zucchi State University of Campinas (UNICAMP) - Brazil
  • Marcos Vinicius Puydinger dos Santos State University of Campinas (UNICAMP) - Brazil
  • Fernando César Rufino State University of Campinas (UNICAMP) - Brazil
  • José Alexandre Diniz State University of Campinas (UNICAMP) - Brazil

Keywords:

Silicon, Nanowire, SiNW, Scaling, Nanosheets

Abstract

The silicon nanowire (SiNW) is poised to become an industry standard on the upcoming technological nodes. It presents improved current drive and modulation, minimized footprint, stackability, and a host of different beneficial characteristics. The last few years of research have focused on solving the last remaining challenges of SiNW fabrication as they roll into commercial usage. Now, novel devices, as well as channel and device stacking for 3D VLSI applications is being studied. As well as how can the SiNW geometry can be harnessed for More Than Moore materials and applications. In this review, we present a sample of the range of devices, techniques and applications of SiNW structures, alongside novel developments in the research carried out at University of Campinas. Demonstrations of JLFETs fabricated using Ga+-FIB, e-beam lithography, silicon etching in NH4OH solution, FinFETs fabricated using Ga+ lithography and strained silicon structures are shown. Promising future developments in VLSI and More Than Moore applications such as vertically stacked nanowire geometries, graphene nanoribbon devices, and MagFETs are also presented.

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Published

2022-09-17

Issue

Section

Special Issue on Emerging Semiconductor Devices