Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures
Keywords:SOI Technology, Nanowires, MOSFET, Cryogenics, High Temperature
This review paper presents the electrical characteristics of Silicon-On-Insulator Ω-Gate nanowires in a wide range of temperatures. The operation in cryogenic and high-temperature environments will be experimentally explored. The influence of nanowire width and channel length will be discussed. Nanowires with and without strain will be investigated from room temperature down to cryogenic ones, showing that strained nanowires improve carrier mobility in the whole temperature range. At high temperatures, it is demonstrated that nanowires can operate successfully up to 580 K, maintaining the ideal body factor. The effect of high temperatures on Gate-Induced Drain Leakage will also be studied. The experimental results in the whole temperature range confirm that SOI nanowires are an excellent alternative for FinFET replacement in future technological nodes.
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