Effect of Lines and Vias Density on the BEOL Temperature Distribution
Keywords:BEOL temperature, thermal conductivity, chip reliability
A method to calculate the temperature distribution on the BEOL structure and its impact on the EM in a design environment has been developed and implemented. The study for a 45 nm technology indicated a large temperature variation from the local to the global interconnects, which should be considered for the EM induced resistance increase of the line, in contrast to the standard analysis through a fixed operation temperature throughout the BEOL. The results show that a significant additional temperature above 50°C exist on the layers M1 to M6 due the power dissipated from transistors. The temperature reduction on the local layer is evaluated increasing the number of vias and enlarging the interconnect lines, both with a direct influence on the BEOL thermal distribution. A reduction of 62.9°C is obtained for M1 layer, considering a fraction volume of 40% for lines and 6% for vias.