Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Authors

  • T. Nagalaxmi Osmania University - India
  • E. Sreenivasa Rao Vasavi College of Engineering - India
  • P.Chandrasekar Osmania University - India

DOI:

https://doi.org/10.29292/jics.v17i3.640

Keywords:

Asynchronous Network on Chip, Clock and data recovery circuit, Metastability, Low power, Multiprocessor System on Chip

Abstract

Today, the current buffered router Synchronous Network on Chip architecture consumes significant chip area and power. Therefore, based on biased routing, buffer-less routers have recently been predicted as a possible solution, but they suffer from contiguous port assignments, slow critical paths, and increased latency. Asynchronous Network on Chip architecture emerges as the best option for avoiding glitches and consuming less power. A clock and data recovery circuit is used to recover the clock signal from the router-generated data and reduce power consumption in a Multiprocessor System on Chip. This paper proposes a clock and data recovery circuit design for an asynchronous Network on Chip. The proposed 4x4 Mesh router architecture implemented in this paper can process 64-bit of data samples with a depth of 64. When comparing the proposed architecture with the existing NoC architecture, the proposed architecture has shown a power reduction of 5times. The proposed architecture has consumed a total power of 0.103W.

Author Biographies

T. Nagalaxmi, Osmania University - India

Department of Electronics and Communication Engineering, Osmania University, Hyderabad, Telangana, India - 500007

E. Sreenivasa Rao, Vasavi College of Engineering - India

Department of Electronics and Communication Engineering, Vasavi College of Engineering, Hyderabad, Telangana, India-500089

P.Chandrasekar, Osmania University - India

Department of Electronics and Communication Engineering, Osmania University, Hyderabad, Telangana, India- 500007

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Published

2022-12-31