Low-Dropout Voltage Regulator Designed with Nanowire TFET with Different Source Composition Experimental Data
Keywords:TFET, nanowire transistors, LUT, low-dropout voltage regulators, analog circuit design
This paper presents the design of low-dropout volt-age regulators (LDO) using nanowire tunnel field-effect tran-sistors (TFETs) and nanowire MOSFET. The devices are mod-eled using lookup tables implemented with experimental measures of TFETs with different source compositions (Si, SiGe and Ge) and MOSFET. In order to compare the designs, the transistors of the differential amplifier in all LDOs is biased with gm/ID = 8 V-1 with a load of 1 μA and 10-pF. It is shown that all TFET based LDOs are stables without the need of a compensator capacitor (CC) even for higher load capacitance. For the MOSFET LDO, a CC of 5-pF capacitor was used. The study shows that the TFET based LDOs deliver higher effi-ciency due to the possibility to operate with low bias current. In the transient analysis it is shown that the TFET LDOs have lower overshoot but higher delay. The Ge-TFET LDO pre-sented settling times for load and line transient close to the MOSFET LDO with 15 μs and 30 μs. The SiGe-TFET LDO shows the best loop gain (60 dB), while the Si-TFET LDO deliv-ers lowest quiescent current (300 pA) and the Ge-TFET have the best GBW (70 KHz) and PSR (-52 dB). It is concluded that the TFET based LDOs can deliver specifications similar or bet-ter than the MOSFET LDO even without the need of CC and with less power consumption.
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