Behavioral and Electrical Modeling of a 0.5-V Third-Order Continuous-Time Sigma-Delta Modulator with FIR DAC for Audio Applications

Authors

  • Matheus Cortez Federal University of Pampa
  • Alessandro Gonçalves Girardi Federal University of Pampa
  • Lucas Compassi Severo Federal University of Pampa
  • Paulo César Comassetto de Aguirre Federal University of Pampa

DOI:

https://doi.org/10.29292/jics.v18i1.664

Keywords:

Sigma-delta, Modulator, Continuous-time, Amplifier, SNDR, ENOB

Abstract

Most mobile and wearable devices present digital audio signal processing capabilities. Since the nature of audio signals is analog, there is a need to use analog-to-digital converters (ADCs) with high-resolution for a high signal-to-noise ratio audio acquisition. This paper presents the high-level modeling and design of a continuous-time third-order sigma-delta modulator (CT-SDM) with an FIR DAC for audio devices, using a supply voltage of 0.5 V. The design is divided in three steps and is carried out using the Delta-sigma toolbox and a discrete-time to continuous-time (DT-CT) transformation. First, the schematic implementation with verilogA models is done to estimate the first-integrator amplifier specifications for the modulator to provide 14 bits of ENOB. Following, a two-stage inverter-based amplifier is designed and used to verify the design strategy. Finally, a transistor-level implementation of OTAs and comparator is done to evaluate the CT-SDM performance. An in-depth analysis and discussion are presented to explain the achieved results with those transistor-level circuits.

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Published

2023-05-22

Issue

Section

Selected Papers from SBCCI 2022