A 1.2GHz Frequency Range, 153.4 dBc/Hz FoM, low Phase Noise, Current Starved Multi-Path Ring VCO

Authors

  • Mohd Ziauddin Jahangir Chaitanya Bharathi Institute of Technology
  • Paidimarry Chandra Sekhar Osmania University College of Engineering

DOI:

https://doi.org/10.29292/jics.v18i1.676

Keywords:

Multipath VCO, MultiPath Ring Oscillator, Current Starved Multipath VCO, Dual input current starved inverter, Low phase noise ring oscillator

Abstract

This article describes the design of a low power, low phase noise, multi-Path ring VCO (MPRVCO) in 90nm CMOS process. The proposed oscillator achieves a tuning range of 1.2GHz operating at 1.65 GHz center frequency, with reduced phase noise of -87.3dBc/Hz at 1MHz offset. The proposed MPRVCO achieves a FoM of 153.4dBc/Hz, consuming 0.657mW power at 1.65GHz frequency. The proposed VCO utilizes Current starving technique for frequency variation. Sub-threshold transistor is used to obtain monotonic and linear frequency tuning characteristics. The proposed VCO is one of the very few Current Starved ring VCOs capable of producing such low phase noise in 90nm CMOS process while operating in GHz frequency range

Author Biography

Paidimarry Chandra Sekhar, Osmania University College of Engineering

Prof. Chandra Sekhar Paidimarry received BE degree from Nagpur University, M.Tech degree from JNTU Hyderabad and PhD from Osmania University in 1991, 1999 and 2009 respectively. He had been awarded with Post Doctoral Fellowship by Shizuoka University, Japan for one year. Prior to joining in teaching, he has eight years of industrial experience of design and development of Embedded Systems. He has been working in the Department of Electronics and Communication Engineering, University College of Engineering, Osmania University, Hyderabad from 2001. He has been elevated as Professor of ECE in 2015. He is served as Head of Department, ECE, Osmania University.  He served as Chairman BOS in ECE Department for two years. He is actively involved in establishing the state of art Laboratories in the Department. He has more than 50 research publications to his credit. He delivered more than 15 invited talks and guest lecturers in various conference and events.  Presently eight Ph.D. students are pursuing their research under his guidance. UGC sanctioned a Major Research Project on GNSS Receiver: Baseband algorithms in FPGA, worth of Rs. 15 Lakh. He received a consultancy project from DLRL worth of 10 Lakh. . He Received another Consultancy project from RCI, “Multi Communication protocols for SDR Appliactions” worth of Rs. 10 lakh.He is currently Principal Investigator for CSIR SRF scheme. He is currently serving as Peer review committee member of DLRL projects and Member, System Engineering, BDL. He is member of Board of Studies in several Engineering colleges. His research interests include Development of high performance Computational Electro-magnetic and efficient FPGA based signal processing algorithms and Design Automation

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Published

2023-05-22

Issue

Vol. 18 No. 1 (2023): Journal of Integrated Circuits and Systems

Section

Regular Papers

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Copyright (c) 2023 Journal of Integrated Circuits and Systems

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