A Design Space Exploration of Power-efficient Gaussian Filter Architectures using Logical Optimization and Approximated Adders

Abstract

Gaussian filtering is an important step in many image-processing applications because it reduces image noise.
However, this step is also compute-intensive, so power-optimized hardware architectures are necessary to allow its adoption in embedded devices. This work presents a design space exploration of power-efficient Gaussian filter architectures.
Differently from related work, this work shows the impacts of the design decisions on two target applications: the Canny Algorithm and an Automatic License Plate Recognition system.
To explore the design space, the 3x3, 5x5, and 7x7kernels were logically refactored using Multiplierless Constant Multiplication and Common Sub-expression Exploration. The adders were approximated using the copy strategy to further reduce power consumption. Systematic experiments show the effects of the adopted strategies on power savings and quality of results compared to exact baselines using the two applications.
The approximate strategy reached up to 51 dB of Peak Signal-to-Noise Ratio with power reductions of up to 48% in the best-case scenario of the standalone Gaussian filters. Also, the total power of the Gaussian filter in the Canny Algorithm can be reduced down to 34% while maintaining the precision of results between 57% and 90%. Finally, the proposed strategies reduce up to 64% of the Gaussian filter power consumption when adopted in the plate detection solution with a similar detection rate compared to the exact filter architecture.