Variable Block Size Fractional Motion Estimation Hardware Architecture for VVC and HEVC Standards

Authors

  • Nicole Citadin Federal University of Santa Catarina
  • Ismael Seidel Federal University of Santa Catarina
  • Mateus Grellert Federal University of Rio Grande do Sul
  • José Luis Güntzel Federal University of Santa Catarina

DOI:

https://doi.org/10.29292/jics.v18i3.787

Keywords:

Video Coding, Fractional Motion Estimation, Versatile Video Coding, High Efficiency Video Coding, Hardware Architecture

Abstract

The ever-increasing growth in digital video consumption motivates the research and development of new video coding standards to improve coding efficiency. Among the several new tools that the Versatile Video Coding (VVC) standard introduced lies the Quadtree Plus Multi-Type Tree (QT+MTT), which improves upon the quadtree of High Efficiency Video Coding (HEVC) in terms of coding efficiency. Nevertheless, such improvements come at the cost of increased complexity. Hence, to meet the real-time and energy efficiency requirements, embedded devices must adopt techniques to effectively reduce the VVC complexity, including customized hardware accelerators. This work presents a low-energy hardware architecture design for the Fractional Motion Estimation (FME), one of the most critical steps of HEVC and VVC encoders. The proposed architecture supports the Switchable Interpolation Filter (SIF) of VVC and was synthesized to enable Variable Block Size (VBS) from 8×8 up to 128×128 sized blocks so that it can perform the FME of most partitions of the QT+MTT from VVC. The results show increases of at most 4.52% in area and 10.79% in total power for the extra hardware needed to support VBS, and up to 9.15% and 15.72%, in area and power, respectively, for supporting up to 128×128 block sizes.

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Published

2023-12-28

Issue

Section

Selected Papers from SForum 2023. Guest Editors: Cristina Meinhardt (UFSC - Brazil) and Germano Penello (USP - Brazil)