High-Throughput Hardware Design for Linear Equation System Solving of VVC Affine Prediction

Authors

  • Denis Maass Universidade Federal de Pelotas
  • Marcello Muñoz Universidade Federal de Pelotas
  • Murilo Perleberg Universidade Federal de Pelotas
  • Luciano Agostini Universidade Federal de Pelotas
  • Marcelo Porto Universidade Federal de Pelotas

DOI:

https://doi.org/10.29292/jics.v18i3.789

Keywords:

VVC, Affine Motion Estimation, Inter prediction, Hardware Design

Abstract

The affine prediction is the main novelty in the inter-frame prediction of Versatile Video Coding (VVC) standard. However, implementing the affine prediction requires a huge computational effort that makes mandatory the use of dedicated hardware accelerators to achieve real-time processing and meet the constraints of area and power dissipation for mobile devices. In light of this, this work presents different approaches for a hardware design dedicated to solving the linear equation system, which is essential for refining
the affine Motion Vector. Synthesis results show that the High- Throughput architecture, which explores the parallelism of internal operations, can reach an accuracy of 99.99%, requiring 333.9kgates to be implemented and presenting a power dissipation of 120.4mW when running at 540MHz, the operational frequency required to process 60 frames per second of HD 1080p videos.

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Published

2023-12-28

Issue

Section

Selected Papers from SForum 2023. Guest Editors: Cristina Meinhardt (UFSC - Brazil) and Germano Penello (USP - Brazil)