Low-Power Inverse Multiple Transform Hardware Design for 8K@60fps Real-Time VVC Decoding

Authors

  • Bruna Garcia Federal University of Pelotas
  • Bianca Silveira UFPel − Brazil
  • Claudio Diniz UFRGS − Brazil
  • Daniel Palomino UFPel − Brazil
  • Guilherme Correa Federal University of Pelotas

DOI:

https://doi.org/10.29292/jics.v18i3.799

Keywords:

Versatile Video Coding, Inverse Transform, Hardware Architecture, ASIC

Abstract

The Versatile Video Coding (VVC) is a new standard released in 2020 and is considered the state-of-the-art technology in video coding. It introduces several innovative tools to achieve high coding efficiency, but, on the other side, requires a significantly higher computational effort. One of the innovations of the standard is the Multiple Transform Selection (MTS), which plays a crucial role in improving coding efficiency. MTS supports square and rectangular transform blocks and includes three transform types (DCT-II, DCT-VIII, and DST-VII) that can be combined in horizontal and vertical directions. As a result, VVC codecs must support a wide range of transform types and formats, making the development of hardware solutions essential to enable real-time processing. This work presents a dedicated hardware architecture for all inverse transforms in the VVC decoder. The proposed architecture performs one-dimensional transforms for all sizes supported in the VVC standard, allowing for the combination into 2D square and rectangular transforms, ranging from 4×4 to 64×64 blocks for IDCT-II and from 4×4 to 32×32 for IDCT-VIII and IDST-VII. The proposed architecture can process videos of up to UHD 8K@60fps resolution in real time, with a power consumption of 778 mW.

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Published

2023-12-28