Framework-based Arithmetic Datapath Generation to Explore Parallel Binary Multipliers

Authors

  • Leandro Mateus Giacomini Rocha Federal University of Rio Grande do Sul (UFRGS) - Brazil
  • Guilherme Paim Federal University of Rio Grande do Sul (UFRGS) - Brazil
  • Gustavo Madeira Santana Federal University of Rio Grande do Sul (UFRGS) - Brazil
  • Eduardo Antônio César da Costa Catholic University of Pelotas (UCPel) - Brazil
  • Sergio Bampi Federal University of Rio Grande do Sul (UFRGS) - Brazil

DOI:

https://doi.org/10.29292/jics.v15i3.91

Keywords:

Parallel Multipliers, Adder Topologies, VLSI Design, ASIC

Abstract

Arithmetic modules usually have a significant impact on performance, circuit area, energy, and power in digital circuits of DSP (Digital Signal Processing). Exploring implementation trade-offs in these circuits is of utmost importance in low-power and low-cost devices such as sensors in IoT devices which often have stringent requirements. Multipliers are of particular concern due to their ubiquitous use in DSP algorithms and their inherent implementation complexity. This work proposes a framework to efficiently generalize and explore different compositions of arithmetic operators with an emphasis on parallel binary multipliers, guiding the designer through the micro-architecture development. Several partial product encoders were combined with multiple compression trees to generate multipliers that were synthesized in a commercial 65 nm to obtain area, power, and timing results.

Additional Files

Published

2020-12-22

Issue

Section

Selected Papers from 34th South Symposium on Microlectronics