Journal of Integrated Circuits and Systems

Impact of the gate work function on the experimental I-V characteristics of MOS solar cells simulated with the Sentaurus TCAD software

Fri, 15 Mar 2024 00:00:00 +0000

In this work, the influence of gate work function on the experimental J-VG characteristics of MOS solar cells was investigated with the aid of the Sentaurus TCAD for 2D numer-ical simulations of TiN/SiOxNy/Si Al/SiOxNy/Si and Al/MgO/Mg/SiOxNy/Si structures aiming at solar cells for en-ergy harvesting applications. The increase of the gate work function led to the increase of the reverse current density as pointed out by the Sentaurus TCAD simulations and by the ex-perimental J-VG characteristics. The work functions of Mg, Al, and un-annealed TiN used in the TCAD simulations were 3.7 eV, 4.1 eV, and 4.4 eV, respectively. It was observed that the onset voltage at 0.5 mA/cm2 in the forward-biasing region was at a lower voltage for TiN (~ - 0.06 V) compared to Al (~ - 0.42 V) and the Al/MgO/Mg stack (~ - 0.47 V). On the other hand, the current density increased steeply in the forward biasing for TiN and Al compared to the Al/ MgO/Mg stack gate and the thin MgO layer between Al and Mg worked as a potential barrier in an opposite direction to the potential barrier of the Mg/Si-OxNy/Si structure, which meant an onset voltage lowering for the Al/MgO/Mg/SiOxNy/Si solar cell. For the Al/MgO/Mg stack, the barrier effect of the MgO layer was fitted as a series re-sistance RS = 100 Ω and an equivalent Al/MgO/Mg work func-tion of 4.15 eV considering a substrate doping NA = 1.2x1016 cm-3 and parallel conductance GP = 0. Also, the experimental JxVG characteristic of the Al/SiOxNy/Si cell was fitted for Al work function of 4.10 eV, a series resistance RS = 100 Ω, a parallel resistance RP = 0.02 Ω (GP = 50 S) and a substrate doping NA = 5.5x1015 cm-3. In this case, the high parallel conductance fitted was attributed to the tunneling through the dielectrics as a pre-dominant effect possibly caused by a high concentration of de-fects in the SiOxNy layer. Finally, the MOS solar cell parameters were relatively lower compared to those of commercial outdoor solar cells, but the power generated by the MOS cells reached the mW range, and the conversion efficiency from light energy into electrical energy was higher (12.7%) than the typical values found for energy-harvesting solar cells.

Design and analysis of Voltage-Gated Spin-Orbit Torque (VgSOT) Magnetic Tunnel Junction based Non-Volatile Flip Flop design for Low Energy Applications

Payal Jangra, Manoj Duhan — Fri, 15 Mar 2024 00:00:00 +0000

In this paper, a Voltage-gated Spin-Orbit Torque based non-volatile flip-flop design has been discussed. The
flip-flop consists of a conventional CMOS master latch used in normal operations, and a VgSOT-MTJ based
slave latch has been considered for interim data saving during power-gating. The current circuit uses the same
write current to write data into two magnetic tunnel junctions, saving 50% of storing energy. The proposed
NVFF circuit has been simulated using Cadence Virtuoso 45nm. The performance parameters like energy
consumption and delay during restore and store operations of VgSOT-MTJ based NVFF circuit have been
analyzed in this paper and compared with SOT-MTJ based and STT-MTJ based NVFF circuits. Simulation
results show that for the switching delay, VgSOT-MTJ based NVFF performs 40% and 58% better than SOT-
MTJ NVFF and STT-MTJ based NVFFs, respectively during storing mode and 83% and 88% better than SOT-
MTJ and STT-MTJ based NVFFs during restoring mode. In terms of energy consumption, during storing
mode, VgSOT-MTJ based NVFF consumes 84% less energy than SOT-MTJ NVFF and 90 % less energy than
STT-MTJ based NVFFs. During restoring mode, VgSOT-MTJ based NVFF consumes 70% and 80% less
energy than SOT-MTJ NVFF and STT-MTJ, respectively.

A Low Power R-peak Detector Clocked at Signal Sampling Rate

Odilon Dutra, Luís H. C. Ferreira, Gustavo D. Colletta, Leonardo B. Zoccal — Fri, 15 Mar 2024 00:00:00 +0000

This paper presents a real-time, low-power R-peak detector implemented in an FPGA. It is different from other implementations as it runs at the same signal sampling rate, rather than utilizing a high clock frequency as utilized in batch processing with high throughput systems. Such implementation relies on a Savitzky-Golay filter for power line noise filtering, and on an adapted version of the Difference Operation Method (DOM) algorithm. The modification in DOM is needed in order to be able to process the data either without increasing the clock to process data in a batch fashion or unsustainably increasing latency. It uses the Savitzky-Golay Digital Differentiator, eliminating further filtering stages. The prototype was characterized using both the MIT-BIH database and Fluke Prosim 8 Vital Signal Simulator. The proposed system features a high degree of matched R-peaks even being extremely efficient regarding power dissipation. Moreover, it shows similar performance when compared to the original Difference Operation Method implementation.
The whole system consumes 260- uW operating at 192-Hz in an FPGA model 10M50DAF484C7G, which belongs to the MAX10 family of Altera devices.

Parameter extraction using the transfer characteristics of vertically stacked Si nanosheet MOSFETs

Fri, 15 Mar 2024 00:00:00 +0000

We present a critical assessment and discussion of the presence of parasitic source-and-drain series resistance and normal electric field-dependent mobility degradation in undoped Si nanosheet MOSFETs. A simple explicit Lambert W function-based closed-form model, continuously valid from sub-threshold to strong conduction, was used to clearly describe the transfer characteristics. The model was applied to experimental vertically stacked GAA undoped Si nanosheet MOSFETs using phenomenon-related model parameter values extracted from measured data through suitable numerical optimization procedures. The conducted analysis reveals and explains how these two effects produce analogous deleterious consequences on these devices’ transfer characteristics.

Improvement of AlGaN/ GaN based HEMT with high performance rate for integrated circuit design for wide range of applications

Swati Dhondiram Jadhav, Aboo Bakar Khan — Fri, 15 Mar 2024 00:00:00 +0000

In the current research work, we focused on the design and analysis of a semiconductor device called High-Elec-tron-Mobility Transistor (HEMT) based on the AlGaN/GaN material system. An Aluminum Nitride spacer,Layer of Nucle-ation along with cap as a AlGaN and barrier of GaN with the channel of AlGaN are incorporated to enhance HEMT device performance.
The electrical characteristics of the proposed HEMT are an-alyzed. The Drain Current is found to be 0.18A/mm, indicating the device's ability to handle high current levels. The Electron Concentration is observed to have a maximum value of -96.12electrons/cm3 and varying based on the position in the channel for GaN Barrier thickness is 0.15mm. In the analysis of AC such as Gain of the Maximum Unilateral Power is deter-mined to be 83.41dB, indicating the ability of the device to am-plify signals. The Y-parameters, which characterize the de-vice's behavior at various frequencies of operation, are also de-termined. The capacitance between the electrode region Gate-Source (CGSMIN) is found to be 1.70×10^-11 F/mm, and alike The Capacitance between the electrode region the Gate-Drain Ca-pacitance (CGDMIN) is determined to be 4.7×10^-12 F/mm. Fur-thermore, an Electric Field of 96.51×10^3 V/mm is observed, in-dicating the strength of the electric field across the device. For HEMT device the simulation,The TCAD Silvaco software is be-ing practiced.

Analysis of biosensing performance of Trench Double Gate Junctionless Field Effect Transistor

PALASRI DHAR, Soumik Poddar, Sunipa Roy — Fri, 15 Mar 2024 00:00:00 +0000

Diversified biomolecules sensing is turning out to be the most promising area of research due to ever decreasing healthy lifestyle. Field effect transistorized biosensing approach puts its signature as label free, portable and also very careful pathway. In this present work a trench structured dielectric modulated double gate junction-less field effect transistor (TG-DMJLFET) is urbanized using SILVACO ATLAS simulator for label free detection of biomolecules. The developed structure has two vertically positioned gates in distinct trenches. For immobilizing biomolecules, two cavities are formed in the gate oxide region for dielectric modulation. The dielectric constant (k) has been varied over a wide range of 1.54 (Uricase) to 12(Gelatin) signifying the sensing of diverse charged biomolecules. The sensitivity is evaluated in terms of threshold voltage shift and transconductance . The in-depth electrostatic analysis is illustrated in terms of central potential ,energy band diagram ,drive current and also by the depiction of the electric field .In case of charged biomolecules, the shift in threshold voltage is obtained as 350 mV for change in the di-electric constant (k) ranging from 1.54 to 12. The transconductance alteration is observed as 1.94×10^-5 when the k is changed from 3.46 to 12 .The device has showed excellent performance in biomolecules sensing.

Design and performance analysis of a MEMS Based Area-Variation Capacitive Accelerometer with Readout Circuit

Mahua Raha Patra, Kalyan Biswas — Fri, 15 Mar 2024 00:00:00 +0000

The structural optimization of the device is used in the present work to demonstrate the improvement of the device sensitivity for a MEMS accelerometer based on capacitive principle due to overlap area change between electrodes. The proof mass of the device is made up of a few parallel fingers those are joined together. Proof mass is supported by flexible mechanical beams that resemble springs is suspended over fixed electrodes and are fastened to the substrate. The greatest displacement that the proof mass can suffer with application of acceleration is determined for the specific construction. The connected beams' width and length were changed, and ANSYS FEA software was used to model the reaction. Sensitivity of the device is analyzed and discussed based on the findings of various device geometry measurements, and suggestions for improving sensitivity are also made. Additionally, a signal conditioning circuit that changes the capacitance to voltage as a result of the proof mass deflecting differently is described. These discoveries might help designers to create capacitive MEMS accelerometers with increased sensitivity.

Efficient 3’s Complement Circuit for Ternary-ALU

Fri, 15 Mar 2024 00:00:00 +0000

Carrying more information makes the ternary-computation effective in order to reduce the interconnect complexity and hence, ternary computer can be the future alternative to conventional (binary) counterpart. As a consequence the ternary arithmetic has become the centre of choice among circuit/system researcher in recent time. Ternary adder/subtractor is the integral part of Ternary Arithmetic Logic Unit (TALU) and the 3’s complement is used to represent negative ternary number in TALU. This work proposes a new two-step low hardware-cost strategy to converts ternary input into its 3’s complement output. Novel hardware optimization using normal process Enhancement-type Metal Oxide Semiconductor (E-MOS)-transistor is explored and exploited to design proposed 4-trit 3’s complement generator on 32nm standard CMOS technology with 0.9V supply-rail at 27°C temperature using typical MOS-transistor. Unbalanced ternary digit “0”, “1” and “2” are denoted with ground, supply/2 and supply respectively. The T-Spice transient simulations with all possible test patterns validate the working of proposed circuit and the corresponding speed-power characteristic is compared with most recent counterpart. The circuit performance is also evaluated with different load condition. The 4-trit 3’s complement circuit is extended next to propose 16-trit 3’s complement generator and the impact of Process and Environmental variation on the proposed circuit is studied.

Improved Sensitivity of MEMS-based Piezoresistive Pressure Sensor using Silicon Nitride Diaphragm

Kakali Das, Himadri S. Dutta — Fri, 15 Mar 2024 00:00:00 +0000

In this paper, Piezoresistive Pressure Sensor (PPS) with four Polysilicon piezoresistors on Si3N4 diaphragm with improved sensitivity is successfully designed by using MEMS technology. Sensing is accomplished via deposited polysilicon resistors like metal resistors. The analytical model of PPS is optimized for location and geometry of the piezoresistors and the sensors based on different aspect ratios (both square and rectangular) have been investigated. The performance parameters like maximum deflection, maximum induced stress on the diaphragm have been compared using ANSYS and MATLAB simulation programming based on mathematical model. By interpreting the proper selection of the geometry of a thin Si3N4 diaphragm, the maximum deflection, maximum induced stress and highest sensitivity for this sensor are obtained for the diaphragm when aspect ratio is minimum. It has been found that sensitivity of the sensor is achieved when the piezoresistors are symmetrically placed at 65 m from the edges of the diaphragm. The analysis describes that the sensor based on square diaphragm is more sensitive than the rectangular one. It is influenced more powerfully by diaphragm thickness. The applied pressure range is considered from 0.5 kPa to 40 kPa. From the simulation results, the shape and the sensor design can be optimized for a highly sensitive PPS.

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

Tejender Singh, Suman Lata Tripathi, Vikram Kumar — Fri, 15 Mar 2024 00:00:00 +0000

In this study, a high-performance 16-bit, 500 MS/s successive approximation register analog-to-digital con-verter (SAR-ADC) with variable body biasing (VBB) for re-ducing sub-threshold leakage is designed and optimized. The suggested ADC architecture makes use of a voltage threshold complementary metal-oxide-semiconductor (VTCMOS) cir-cuit with Widlar current mirror technology to efficiently con-sume 39.2 μW at an operating voltage of 1.0 V. Notably, the optimized ADC achieves outstanding performance measures, such as a signal-to-noise and distortion ratio (SNDR) of 97 dB and a total harmonic distortion (THD) of -97.97 dB, which are crucial markers of the ADC's accuracy and fidelity. An over-view of the growing need for high-resolution ADCs in contem-porary high-speed data conversion systems opens the study. The main goal of this effort is to improve overall ADC per-formance and tackle the problem of sub-threshold leakage. The Widlar current mirror technology and the VTCMOS cir-cuit are integrated for enhanced linearity, decreased current mismatch errors, and minimized leakage current. This inte-gration is highlighted in the full explanation of the ADC de-sign. The advent of the VBB approach as a successful method of leakage reduction is a significant contribution to this re-search. The theoretical foundations and workings of the VBB technique are discussed, and thorough simulations and tests are used to assess how the VBB technique affects leakage cur-rent and circuit performance. The SAR-ADC design and simulations were carried out using Cadence Virtuoso soft-ware.

Dynamic Automation of a Moving Vehicle at Real time along with Position and Condition Tracking

Soumen Santra, Shruti Sinha, Arpan Deyasi — Fri, 15 Mar 2024 00:00:00 +0000

The present work deals with real-time database updation of moving vehicle through dynamic automation system, where position and internal conditions of the car are auto-saved in the cloud server. The total embedded system is a simulated prototype, already implemented virtually for smaller distance movement on suitable road condition, where the auto-checking of the fuel remained shows the novelty of the system compared to the existing data available in literature. As evident form experimental results, soil moistures sensor detects the road condition, whereas ultrasonic helps to reduce the accident probability with real-time tracking. Humidity and temperature sensors also give real-time environmental condition outside the car which is crucial while driving at extreme climatic condition. Insurance companies as beneficiaries also check the status of it if the car is suffered from accidents or unnecessary external coercive influences. Data display facility is available at real time to avoid any unwanted proximity with nearby moving/standing objects, and later can be retrieved from the secured database. The work may be extended as a complete autonomous tracker with condition monitor in future automobile industry.

Design and Performance Assessment of a Label- free Biosensor utilizing a Novel TFET Configuration

Rapolu Anil Kumar, Girija Sravani K, K. Srinivasa Rao — Fri, 15 Mar 2024 00:00:00 +0000

The present study presents an innovative idea: an original design for a label-free biosensor utilizing H-shape channel configuration within a dielectrically modulated (DM) double-gate TFET (DGTFET) framework, which includes the incorporation of a drain pocket (DP). This design concept is introduced In this study, an analytical model for the DM DPDG-TFET has been created for the first time was formulated and subsequently verified through comparison with industry-standard simulation software (Silvaco TCAD). In this paper we have examine both the biosensor's sensitivity and its effectiveness when employed as a tunnel field-effect transistor (TFET) device. A comprehensive analysis of the device's performance has been conducted. The innovative configuration of the suggested TFET results in heightened sensitivity. Incorporating a drain pocket (DP) at the junction between the drain and channel effectively eliminates ambipolarity, showcasing a successful approach. The H-shape DM DPDGTFET design demonstrates its superiority over various devices documented in the literature. The presence or lack of electric charge in various biomolecules is examined in order to evaluate the device's sensitivity as a label-free biosensor.

Alternative approach to design Dibit-based XOR and XNOR gate

Surajit Bosu, Baibaswata Bhattacharjee — Fri, 15 Mar 2024 00:00:00 +0000

In this generation, high-speed communication has very demanding. In this respect, optical communication plays a crucial role in meeting the goal of high-speed communication. With the increasing demands of high-speed communication, huge data processing is also needed. Therefore, we have proposed a design of XOR and XNOR gates using five reflective semiconductor optical amplifiers (RSOA). Our proposed gates are dibit logic-based. To increase the reliability of the devise, we have incorporated this logic scheme. Here, we consider the logic state ‘0’ for the absence of pulse and logic state ‘1’ for the presence of pulse. The dibit logic ‘0 1’ and ‘1 0’ are similar as ‘0’ and ‘1’ in digtal states, respectively. To check its practical feasibility, we have simulated the proposed design in Matlab
software and also quality factor, contrast, and extinction ratios are calculated for this design.

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

Mainak Mukherjee, Niloy Ghosh, Papiya Debnath, A Sarkar, MANASH CHANDA — Fri, 15 Mar 2024 00:00:00 +0000

In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.

Small-Signal Modeling and Parameter Extraction Method for Photovoltaic Cell Integration in Indoor Visible Light Communication Systems

Fri, 15 Mar 2024 00:00:00 +0000

Photovoltaic (PV) cells are being adopted as a viable and cost-effective option for implementing receivers within Visible Light Communication (VLC) systems, primarily in indoor environments. Accurately estimating the generated current and voltage of the PV cell based on incident light is crucial when designing VLC systems.
For this assessment, the 1D2R electrical equivalent model, which incorporates a diode and two resistors, is employed.
In AC small signal analysis, the diode is substituted by its dynamic counterpart, which comprises a dynamic resistance in parallel with an equivalent capacitance. This study introduces an approach to measure and characterize the small-signal parameters of a PV cell operating at the maximum power point (MPP), open circuit (OC), and short circuit (SC) bias points. This is achieved through a closed-loop frequency response system, calibrated to encompass illuminance levels ranging from 50 to 500 lux.
The procedure for estimating the AC response of the PV cell is outlined, and the outcomes are subsequently employed in an analytical parameter extraction methodology. Experimental results from a 20 x 40 mm PV cell reveal that MPP represents the least favorable bias point in terms of bandwidth, whereas the SC bias point exhibits the most favorable performance. This observation validates the hypothesis that the optimal bias point for energy harvesting in PV cells is the worst bias point for communication purposes.

Comparative Implementation of PicoSoC System-on-Chip in X-Fab 180 nm CMOS Technology

Rodrigo Wuerdig, Leonardo H. Brendler, Cláudio Diniz, Ricardo Reis, Sergio Bampi — Fri, 15 Mar 2024 00:00:00 +0000

This paper presents the physical implementation of the PicoSoC System-on-Chip (SoC) using commercial EDA tools, to use it as a comparison source for future advances in open-source EDA tools for digital implementation flows. The PICORV32 is a simple and versatile microcontroller core that can be used for different applications (e.g., Internet of Things). The whole process entails logical and physical synthesis, design goals aspects, and reports by tools under different working conditions. The Logical and Physical synthesis of the PicoSoC for the X-Fab 180 nm node technology, presented in this work, relies on using the Cadence EDA tools. The microcontroller
core was fully synthesized with and without pads, resulting in a SoC that, including the pads, presents an estimated energy consumption of about 695.3 pJ per operation under nominal conditions.